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EBJ21UE8BFU0-GN-F 参数 Datasheet PDF下载

EBJ21UE8BFU0-GN-F图片预览
型号: EBJ21UE8BFU0-GN-F
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB DDR3 SDRAM SO- DIMM [2GB DDR3 SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 16 页 / 247 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBJ21UE8BFU0  
CKE (input pins)  
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.  
Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down  
(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the  
power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper  
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read  
and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,  
excluding CKE, are disabled during self-refresh.  
DQ (input and output pins)  
Bi-directional data bus.  
DQS and /DQS (input and output pins)  
Output with read data, input with write data. Edge-aligned with read data, centered in write data.  
The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during  
READs and WRITEs.  
ODT (input pins)  
ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only  
applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to  
disable ODT.  
DM (input pins)  
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.  
VDD (power supply pins)  
1.5V is applied. (VDD is for the internal circuit.)  
VDDSPD (power supply pin)  
3.3V is applied (For serial EEPROM).  
VSS (power supply pins)  
Ground is connected.  
VTT (power supply pins)  
I/O termination supply for SDRAM.  
VREFDQ (power supply pin)  
Reference voltage for DQ.  
VREFCA (power supply pin)  
Reference voltage for CA.  
/RESET (input pin)  
/RESET is negative active signal (active low) and is referred to VSS.  
Data Sheet E1642E30 (Ver. 3.0)  
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