欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBE51UD8AGWA 参数 Datasheet PDF下载

EBE51UD8AGWA图片预览
型号: EBE51UD8AGWA
PDF下载: 下载PDF文件 查看货源
内容描述: 512MB无缓冲DDR2 SDRAM DIMM [512MB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 25 页 / 234 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE51UD8AGWA的Datasheet PDF文件第7页浏览型号EBE51UD8AGWA的Datasheet PDF文件第8页浏览型号EBE51UD8AGWA的Datasheet PDF文件第9页浏览型号EBE51UD8AGWA的Datasheet PDF文件第10页浏览型号EBE51UD8AGWA的Datasheet PDF文件第12页浏览型号EBE51UD8AGWA的Datasheet PDF文件第13页浏览型号EBE51UD8AGWA的Datasheet PDF文件第14页浏览型号EBE51UD8AGWA的Datasheet PDF文件第15页  
EBE51UD8AGWA  
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)  
Parameter  
Symbol  
Grade  
max.  
Unit  
Test condition  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Operating current  
(ACT-PRE)  
-6E  
-5C  
920  
880  
IDD0  
mA  
one bank; IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
(ACT-READ-PRE)  
-6E  
-5C  
1040  
1000  
IDD1  
mA  
all banks idle;  
tCK = tCK (IDD);  
Precharge power-down  
standby current  
-6E  
-5C  
80  
80  
IDD2P  
IDD2Q  
IDD2N  
mA  
mA  
mA  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
all banks idle;  
tCK = tCK (IDD);  
Precharge quiet standby  
current  
-6E  
-5C  
200  
200  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
all banks idle;  
tCK = tCK (IDD);  
-6E  
-5C  
280  
240  
Idle standby current  
CKE is H, /CS is H;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
all banks open;  
Fast PDN Exit  
tCK = tCK (IDD);  
MRS(12) = 0  
CKE is L;  
-6E  
-5C  
320  
320  
IDD3P-F  
IDD3P-S  
mA  
mA  
Active power-down  
standby current  
Other control and address bus  
-6E  
-5C  
200  
200  
Slow PDN Exit  
MRS(12) = 1  
inputs are STABLE;  
Data bus inputs are FLOATING  
all banks open;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-6E  
-5C  
560  
520  
Active standby current  
IDD3N  
IDD4R  
mA  
mA  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
Operating current  
(Burst read operating)  
-6E  
-5C  
1840  
1520  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
Operating current  
(Burst write operating)  
-6E  
-5C  
1760  
1520  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
IDD4W  
mA  
Preliminary Data Sheet E0921E10 (Ver. 1.0)  
11  
 复制成功!