EBE41EF8ABFA
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A14 (input pins)
Row address (AX0 to AX14) is determined by the A0 to the A14 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address
becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0, BA1, BA2 (input pin)
BA0, BA1 and BA2 are bank select signals (BA). The memory array is divided into 8 banks: bank 0 to bank 7. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
BA2
L
Bank 0
Bank 1
H
L
L
L
Bank 2
H
H
L
L
Bank 3
H
L
L
Bank 4
H
H
H
H
Bank 5
H
L
L
Bank 6
H
H
Bank 7
H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1285E10 (Ver. 1.0)
26
ELPIDA [ ELPIDA MEMORY ]
