EBE41EF8ABFA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8G
-6E
Speed bin
Parameter
DDR2-800 (6-6-6)
min.
DDR2-667 (5-5-5)
min.
Symbol
tRCD
tRP
max.
max.
Unit
ns
Notes
Active to read or write command
delay
15
15
Precharge command period
15
15
ns
Active to active/auto-refresh
command time
tRC
60
60
ns
DQ output access time from CK, /CK tAC
DQS output access time from CK,
/CK
−400
−350
+400
+350
−450
−400
+450
+400
ps
10
10
tDQSCK
ps
tCK
(avg)
CK high-level width
tCH (avg) 0.48
0.52
0.52
0.48
0.48
0.52
0.52
13
tCK
(avg)
CK low-level width
CK half period
tCL(avg)
tHP
0.48
13
Min. (tCL(abs),
tCH(abs))
Min.(tCL(abs),
tCH(abs))
ps
ps
6, 13
13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
3000
8000
(CL = 5)
tCK (avg) 3000
tCK (avg) 3750
tCK (avg) 5000
tDH (base) 125
tDS (base) 50
8000
8000
8000
3000
3750
5000
175
8000
8000
8000
ps
ps
ps
ps
ps
13
13
13
5
(CL = 4)
(CL = 3)
DQ and DM input hold time
DQ and DM input setup time
100
4
Control and Address input pulse
width for each input
tCK
(avg)
tIPW
tDIPW
tHZ
0.6
0.6
DQ and DM input pulse width for
each input
tCK
(avg)
0.35
0.35
Data-out high-impedance time from
CK,/CK
tAC max.
tAC max. ps
10
DQS, /DQS low-impedance time from
CK,/CK
tLZ (DQS) tAC min.
tAC max.
tAC max.
200
tAC min.
tAC max. ps
tAC max. ps
10
10
DQ low-impedance time from CK,/CK tLZ (DQ)
2 × tAC min.
2 × tAC min.
DQS-DQ skew for DQS and
tDQSQ
240
340
ps
associated DQ signals
DQ hold skew factor
tQHS
300
ps
ps
7
8
DQ/DQS output hold time from DQS tQH
DQS latching rising transitions to
associated clock edges
tHP – tQHS
tHP – tQHS
tCK
(avg)
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK
(avg)
DQS input high pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
0.35
0.35
0.2
0.2
2
tCK
(avg)
DQS input low pulse width
tCK
(avg)
DQS falling edge to CK setup time
tCK
(avg)
DQS falling edge hold time from CK tDSH
Mode register set command cycle
time
tMRD
nCK
Preliminary Data Sheet E1285E10 (Ver. 1.0)
18
ELPIDA [ ELPIDA MEMORY ]
