EBE41EF8ABFA
Parameter
Symbol Grade
max.
Unit
mA
Test condition
Auto-refresh current
(Another rank is in IDD2P)
-8G
IDD5
2655
2475
-6E
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current
(Another rank is in IDD3N)
-8G
IDD5
3060
2835
mA
mA
-6E
Self Refresh Mode;
CK and /CK at 0V;
CKE ≤ 0.2V;
Self-refresh current
IDD6
270
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
Operating current
-8G
IDD7
2745
2610
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
mA
mA
(Bank interleaving)
(Another rank is in IDD2P)
-6E
Operating current
-8G
IDD7
3150
2970
(Bank interleaving)
(Another rank is in IDD3N)
-6E
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
Preliminary Data Sheet E1285E10 (Ver. 1.0)
13
ELPIDA [ ELPIDA MEMORY ]
