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EBE41EF8ABFA 参数 Datasheet PDF下载

EBE41EF8ABFA图片预览
型号: EBE41EF8ABFA
PDF下载: 下载PDF文件 查看货源
内容描述: 4GB无缓冲DDR2 SDRAM DIMM [4GB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 30 页 / 242 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE41EF8ABFA  
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)  
Parameter  
Symbol Grade  
max.  
Unit  
mA  
Test condition  
Operating current  
(ACT-PRE)  
(Another rank is in IDD2P)  
-8G  
IDD0  
900  
855  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-6E  
Operating current  
(ACT-PRE)  
(Another rank is in IDD3N)  
-8G  
IDD0  
1305  
1215  
mA  
mA  
-6E  
one bank; IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
Operating current  
-8G  
IDD1  
1035  
990  
(ACT-READ-PRE)  
(Another rank is in IDD2P)  
-6E  
tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
-8G  
IDD1  
1440  
1350  
mA  
mA  
(ACT-READ-PRE)  
(Another rank is in IDD3N)  
-6E  
all banks idle;  
tCK = tCK (IDD);  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge power-down  
standby current  
IDD2P  
270  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge quiet standby  
current  
-8G  
IDD2Q  
630  
540  
mA  
mA  
-6E  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-8G  
IDD2N  
720  
630  
Idle standby current  
-6E  
all banks open;  
Fast PDN Exit  
IDD3P-F  
IDD3P-S  
630  
360  
mA  
mA  
tCK = tCK (IDD);  
MRS(12) = 0  
Active power-down  
standby current  
CKE is L;  
Other control and address bus  
inputs are STABLE;  
Data bus inputs are FLOATING  
Slow PDN Exit  
MRS(12) = 1  
all banks open;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-8G  
IDD3N  
1080  
990  
Active standby current  
mA  
-6E  
Operating current  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
-8G  
IDD4R  
1665  
1485  
mA  
mA  
mA  
mA  
(Burst read operating)  
(Another rank is in IDD2P)  
-6E  
Operating current  
-8G  
IDD4R  
2070  
1845  
(Burst read operating)  
(Another rank is in IDD3N)  
-6E  
Data pattern is same as IDD4W  
Operating current  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-8G  
IDD4W  
1665  
1485  
(Burst write operating)  
(Another rank is in IDD2P)  
-6E  
Operating current  
-8G  
IDD4W  
2070  
1845  
(Burst write operating)  
(Another rank is in IDD3N)  
-6E  
Preliminary Data Sheet E1285E10 (Ver. 1.0)  
12  
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