EBE21FE8ACWT
Reference Clock Input Specifications*1
Parameter
Symbol
min.
max.
Units
MHz
Notes
2, 3, 4
Reference clock frequency@ 4.0 Gb/s
(nominal 166.67MHz)
fRefclk-4.0
158.33
166.75
1.15
Single-ended maximum voltage
Single-ended minimum voltage
Differential voltage high
Differential voltage low
Absolute crossing point
VCross variation
Vmax
V
5, 7
5, 8
6
Vmin
−0.3
V
VRefclk-diff-ih
VRefclk-diff-il
VCross
150
mV
mV
mV
mV
mV
−150
550
140
225
6
250
0.6
5, 9, 10
5, 9, 11
12
VCross-delta
VSCK-cm-acp-p
AC common mode
ERRefclk-diff-Rise,
ERRefclk-diff-Fall
Rising and falling edge rates
4.0
20
V/ns
%
6, 13
6, 14
% Mismatch between rise and fall edge
rates
ERRefclk-Match
Duty cycle of reference clock
Ringback voltage threshold
Allowed time before ringback
Clock leakage current
TRefclk-Dutycycle
VRB-diff
40
60
%
6
−100
100
mV
ps
6, 15
6, 15
16, 17
17
TStable
500
−10
0.5
II_CK
10
µA
pF
Clock input capacitance
CI_CK
2.0
Difference between
RefClk and RefClk#
input capacitance
Clock input capacitance delta
Transport delay
CI_CK (∆)
−0.25
0.25
5
pF
ns
TD
18, 19
NSAMPLE
TREF-JITTER-RMS
1012
periods 20
Reference clock jitter (rms), filtered
3.0
30
ps
ps
21, 22
Reference clock jitter (peak-to-peak) due
to spectrum clocking effects
TREF-SSCp-p
Reference clock jitter difference between TREF-JITTER-
adjacent AMB DELTA
0.75
ps
23
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times
the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FB-
DIMM channel and so on.
3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency.
4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only
required for those data rates that are supported by the device under test.
5. Measurement taken from single-ended waveform.
6. Measurement taken from differential waveform.
7. Defined as the maximum instantaneous voltage including overshoot.
8. Defined as the minimum instantaneous voltage including undershoot.
9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+
equals the falling edge of REFCLK-.
10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing. Refers to all crossing points for this measurement.
11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the
maximum allowed variance in for any particular system.
12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock
frequency).
Data Sheet E1381E10 (Ver. 1.0)
12
ELPIDA [ ELPIDA MEMORY ]
