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EBE21EE8ABFA-4A-E 参数 Datasheet PDF下载

EBE21EE8ABFA-4A-E图片预览
型号: EBE21EE8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB无缓冲DDR2 SDRAM DIMM [2GB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 27 页 / 217 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE21EE8ABFA  
Parameter  
Symbol Grade  
-8E  
max.  
Unit  
mA  
Test condition  
3240  
3105  
2970  
2880  
Auto-refresh current  
(Another rank is in IDD2P)  
-6E  
-5C  
IDD5  
tCK = tCK (IDD);  
-4A  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
-8E  
3960  
3735  
3465  
3285  
Auto-refresh current  
(Another rank is in IDD3N)  
-6E  
IDD5  
mA  
mA  
-5C  
-4A  
Self Refresh Mode;  
CK and /CK at 0V;  
CKE 0.2V;  
Self-refresh current  
IDD6  
216  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
-8E  
-6E  
-5C  
-4A  
3150  
2925  
2880  
2790  
Operating current  
all bank interleaving reads, IOUT = 0mA;  
IDD7  
mA  
mA  
(Bank interleaving)  
(Another rank is in IDD2P)  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
-8E  
3870  
3555  
3375  
3195  
Operating current  
-6E  
IDD7  
(Bank interleaving)  
(Another rank is in IDD3N)  
-5C  
-4A  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD  
values must be met with all combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
Preliminary Data Sheet E0907E10 (Ver. 1.0)  
13  
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