EBE21EE8ABFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol Grade
-8E
max.
Unit
mA
Test condition
1080
990
945
900
Operating current
(ACT-PRE)
(Another rank is in IDD2P)
-6E
-5C
IDD0
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-4A
-8E
1800
1620
1440
1305
Operating current
(ACT-PRE)
(Another rank is in IDD3N)
-6E
IDD0
mA
mA
mA
-5C
-4A
-8E
1215
1125
1080
1035
Operating current
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
-6E
IDD1
(ACT-READ-PRE)
(Another rank is in IDD2P)
-5C
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
-4A
-8E
1935
1755
1575
1440
Operating current
-6E
IDD1
(ACT-READ-PRE)
(Another rank is in IDD3N)
-5C
-4A
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge power-down
standby current
IDD2P
180
mA
mA
mA
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-8E
-6E
-5C
-4A
720
630
540
540
Precharge quiet standby
current
IDD2Q
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-8E
810
720
630
540
-6E
IDD2N
Idle standby current
-5C
-4A
-8E
-6E
IDD3P-F
-5C
720
630
540
540
all banks open;
Fast PDN Exit
mA
mA
tCK = tCK (IDD);
MRS(12) = 0
Active power-down
standby current
CKE is L;
Other control and address bus
-4A
inputs are STABLE;
Data bus inputs are FLOATING
Slow PDN Exit
MRS(12) = 1
IDD3P-S
360
all banks open;
-8E
-6E
-5C
-4A
1620
1440
1170
990
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active standby current
IDD3N
mA
-8E
2115
1845
1575
1350
Operating current
-6E
IDD4R
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA
mA
mA
mA
(Burst read operating)
(Another rank is in IDD2P)
-5C
-4A
-8E
2835
2475
2070
1755
Operating current
-6E
IDD4R
(Burst read operating)
(Another rank is in IDD3N)
Data pattern is same as IDD4W
-5C
-4A
-8E
2115
1845
1575
1350
Operating current
-6E
IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
(Burst write operating)
(Another rank is in IDD2P)
-5C
-4A
-8E
2835
2475
2070
1755
Operating current
-6E
IDD4W
(Burst write operating)
(Another rank is in IDD3N)
-5C
-4A
Preliminary Data Sheet E0907E10 (Ver. 1.0)
12
ELPIDA [ ELPIDA MEMORY ]
