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EBE11UD8AGFA-4A-E 参数 Datasheet PDF下载

EBE11UD8AGFA-4A-E图片预览
型号: EBE11UD8AGFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 64位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 23 页 / 202 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11UD8AGFA  
-6E  
667  
-5C  
533  
min.  
45  
-4A  
400  
min.  
40  
Frequency (Mbps)  
Parameter  
Symbol min.  
max.  
max.  
max.  
Unit  
ns  
Notes  
Active to precharge command tRAS  
45  
70000  
70000  
70000  
Active to auto-precharge  
delay  
tRAP  
tRCD min.  
tRCD min.  
tRCD min.  
ns  
Active bank A to active bank  
tRRD  
7.5  
15  
7.5  
15  
7.5  
15  
ns  
B command period  
Write recovery time  
tWR  
ns  
Auto precharge write  
recovery + precharge time  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
tDAL  
tCK  
1
Internal write to read  
command delay  
tWTR  
tRTP  
7.5  
7.5  
7.5  
10  
ns  
Internal read to precharge  
command delay  
7.5  
7.5  
ns  
Exit self refresh to a non-read  
command  
tXSNR tRFC + 10  
tXSRD 200  
tRFC + 10  
tRFC + 10  
ns  
Exit self refresh to a read  
command  
200  
2
200  
2
tCK  
tCK  
tCK  
Exit precharge power down to  
any non-read command  
tXP  
2
2
Exit active power down to  
read command  
tXARD  
2
2
3
Exit active power down to  
read command  
tXARDS 7AL  
6 AL  
6 AL  
tCK  
2, 3  
(slow exit/low power mode)  
CKE minimum pulse width  
(high and low pulse width)  
tCKE  
tOIT  
3
3
3
tCK  
ns  
Output impedance test driver  
delay  
0
12  
0
12  
0
12  
Auto refresh to active/auto  
refresh command time  
tRFC  
105  
105  
105  
ns  
Average periodic refresh  
interval  
(0°C TC +85°C)  
tREFI  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
µs  
µs  
ns  
(+85°C < TC +95°C)  
tREFI  
Minimum time clocks remains  
ON after CKE  
asynchronously drops low  
tIS + tCK +  
tIH  
tIS + tCK +  
tIH  
tIS + tCK +  
tIH  
tDELAY  
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.  
2. AL: Additive Latency.  
3. MRS A12 bit defines which active power down exit timing to be applied.  
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.  
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.  
CK  
DQS  
/CK  
/DQS  
tIS  
tIH  
tIS  
tIH  
tDS tDH  
tDS tDH  
VDDQ  
VDDQ  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
Input Waveform Timing 1 (tDS, tDH)  
Input Waveform Timing 2 (tIS, tIH)  
Data Sheet E0782E20 (Ver. 2.0)  
17  
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