EBE11UD8AJUA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
Parameter
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
Symbol min.
max.
min.
15
max.
min.
15
max.
Unit Notes
Active to read or write command
delay
tRCD
tRP
12.5
12.5
57.5
ns
ns
ns
Precharge command period
15
15
Active to active/auto-refresh
command time
tRC
60
60
DQ output access time from CK,
/CK
tAC
−400
+400
+350
0.52
0.52
−400
−350
0.48
0.48
+400
+350
0.52
0.52
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
ps
10
10
13
13
DQS output access time from
CK, /CK
tDQSCK −350
tCK
(avg)
CK high-level width
CK low-level width
tCH (avg) 0.48
tCK
(avg)
tCL(avg) 0.48
Min.
Min.
Min.
CK half period
tHP
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
ps
ps
6, 13
13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
2500
8000
3000
8000
(CL = 5)
(CL = 4)
(CL = 3)
tCK (avg) 2500
tCK (avg) 3750
tCK (avg) 5000
8000
8000
8000
3000
3750
5000
8000
8000
8000
3000
3750
5000
8000
8000
8000
ps
ps
ps
13
13
13
tDH
(base)
DQ and DM input hold time
DQ and DM input setup time
125
125
50
175
100
0.6
ps
ps
5
4
tDS
(base)
50
Control and Address input pulse
width for each input
tCK
(avg)
tIPW
tDIPW
tHZ
0.6
0.6
0.35
DQ and DM input pulse width for
each input
tCK
(avg)
0.35
0.35
Data-out high-impedance time
from CK,/CK
tAC max.
tAC max.
tAC max. ps
tAC max. ps
tAC max. ps
10
10
10
DQS, /DQS low-impedance time tLZ
tAC min.
tAC max. tAC min.
tAC max. tAC min.
from CK,/CK
(DQS)
DQ low-impedance time from
CK,/CK
2 ×
tAC min.
2 ×
tAC max.
2 ×
tAC max.
tLZ (DQ)
tAC min.
tAC min.
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
tQHS
tQH
200
300
200
300
240
340
ps
ps
ps
DQ hold skew factor
7
8
DQ/DQS output hold time from
DQS
tHP –
tQHS
tHP –
tQHS
tHP –
tQHS
DQS latching rising transitions to
associated clock edges
tCK
(avg)
tDQSS
−0.25
+0.25
−0.25
0.35
0.35
0.2
+0.25
−0.25
0.35
0.35
0.2
+0.25
tCK
(avg)
DQS input high pulse width
DQS input low pulse width
tDQSH 0.35
tCK
(avg)
tDQSL
tDSS
0.35
0.2
DQS falling edge to CK setup
time
tCK
(avg)
Data Sheet E1083E20 (Ver. 2.0)
16
ELPIDA [ ELPIDA MEMORY ]
