欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBE10RD4ABFA-4C 参数 Datasheet PDF下载

EBE10RD4ABFA-4C图片预览
型号: EBE10RD4ABFA-4C
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 22 页 / 171 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第8页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第9页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第10页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第11页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第13页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第14页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第15页浏览型号EBE10RD4ABFA-4C的Datasheet PDF文件第16页  
EBE10RD4ABFA  
Parameter  
Symbol Grade  
max  
Unit  
mA  
Test condition  
tCK = tCK (IDD);  
-5C  
5030  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
IDD5  
-4A, -4C  
4630  
150  
Self Refresh Mode;  
CK and /CK at 0V;  
CKE 0.2V;  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
Self-refresh current  
IDD6  
IDD7  
mA  
mA  
all bank interleaving reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tRCD = 1 × tCK (IDD);  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
-5C  
6250  
5770  
Operating current  
(Bank interleaving)  
-4A, -4C  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD  
values must be met with all combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
AC Timing for IDD Test Conditions  
For purposes of IDD testing, the following parameters are to be utilized.  
DDR2-533  
DDR2-400  
Parameter  
4-4-4  
4
3-3-3  
3
4-4-4  
4
Unit  
tCK  
ns  
CL(IDD)  
tRCD(IDD)  
15  
15  
20  
tRC(IDD)  
60  
60  
65  
ns  
tRRD(IDD)-×4/×8  
tRRD(IDD)- ×16  
tCK(IDD)  
7.5  
10  
7.5  
10  
7.5  
10  
ns  
ns  
3.75  
45  
5
5
ns  
tRAS(min.)(IDD)  
tRAS(max.)(IDD)  
tRP(IDD)  
45  
45  
ns  
70000  
15  
70000  
15  
70000  
20  
ns  
ns  
tRFC(IDD)  
105  
105  
105  
ns  
Preliminary Data Sheet E0366E50 (Ver. 5.0)  
12