EBD52UC8AKFA-5-E
Timing Parameter Measured in Clock Cycle for Unbuffered DIMM
Number of clock cycle
5ns
tCK
Parameter
Symbol
tWPD
tRPD
min.
max.
—
Unit
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
Burst stop command to write command delay
Burst stop command to DQ High-Z
4 + BL/2
BL/2
2 + BL/2
3
tCK
tCK
—
tCK
tCK
tCK
tCK
tWRD
tBSTW
tBSTZ
—
—
3
3
Read command to write command delay
(to output all data)
tRWD
3 + BL/2
—
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Pre-charge command to High-Z
Write command to data in latency
Write recovery
tHZP
3
3
tWCD
tWR
1
1
3
—
0
DM to data in latency
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
0
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
2
—
—
—
1
15
200
1
Power down exit to command input
1
—
Preliminary Data Sheet E0601E10 (Ver. 1.0)
14
ELPIDA [ ELPIDA MEMORY ]
