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EBD52UC8AKFA-5-E 参数 Datasheet PDF下载

EBD52UC8AKFA-5-E图片预览
型号: EBD52UC8AKFA-5-E
PDF下载: 下载PDF文件 查看货源
内容描述: 512MB无缓冲DDR SDRAM DIMM ( 64M字× 64位, 2级) [512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 188 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD52UC8AKFA-5-E  
Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)  
Parameter  
Symbol  
CI1  
Pins  
max.  
90  
Unit  
pF  
Note  
Address, /RAS, /CAS, /WE,  
/CS, CKE  
CK, /CK  
Input capacitance  
Input capacitance  
CI2  
60  
pF  
Data and DQS input/output  
capacitance  
CO  
DQ, DQS, DM  
15  
pF  
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)  
(DDR SDRAM Component Specification)  
-5B  
min.  
5
-5C  
min.  
5
Parameter  
Symbol  
tCK  
max.  
8
max.  
8
Unit  
ns  
Notes  
Clock cycle time  
CK high-level width  
CK low-level width  
10  
tCH  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tCK  
tCK  
tCL  
min  
(tCH, tCL)  
min  
(tCH, tCL)  
CK half period  
tHP  
tCK  
DQ output access time from CK, /CK  
DQS output access time from CK, /CK  
DQS to DQ skew  
tAC  
–0.7  
0.7  
0.55  
0.4  
–0.7  
0.7  
0.55  
0.4  
ns  
ns  
ns  
ns  
ns  
2, 11  
2, 11  
3
tDQSCK  
tDQSQ  
tQH  
–0.55  
–0.55  
DQ/DQS output hold time from DQS  
tHP – tQHS  
tHP – tQHS  
Data hold skew factor  
tQHS  
0.5  
0.5  
Data-out high-impedance time  
from CK, /CK  
Data-out low-impedance time  
from CK, /CK  
tHZ  
tLZ  
0.7  
0.7  
0.7  
0.7  
ns  
ns  
5, 11  
6, 11  
–0.7  
–0.7  
Read preamble  
tRPRE  
tRPST  
tDS  
0.9  
0.4  
0.4  
0.4  
1.75  
0
1.1  
0.6  
0.9  
0.4  
0.4  
0.4  
1.75  
0
1.1  
0.6  
tCK  
tCK  
ns  
Read postamble  
DQ and DM input setup time  
DQ and DM input hold time  
DQ and DM input pulse width  
Write preamble setup time  
Write preamble  
8
8
7
tDH  
ns  
tDIPW  
tWPRES  
tWPRE  
tWPST  
ns  
ns  
0.25  
0.4  
0.25  
0.4  
tCK  
tCK  
Write postamble  
0.6  
0.6  
9
Write command to first DQS latching  
transition  
tDQSS  
0.72  
1.28  
0.72  
1.28  
tCK  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
DQS input high pulse width  
tDSS  
tDSH  
tDQSH  
tDQSL  
tIS  
0.2  
0.2  
0.35  
0.35  
0.6  
0.6  
2.2  
2
0.2  
0.2  
0.35  
0.35  
0.6  
0.6  
2.2  
2
tCK  
tCK  
tCK  
tCK  
ns  
DQS input low pulse width  
Address and control input setup time  
Address and control input hold time  
Address and control input pulse width  
Mode register set command cycle time  
Active to Precharge command period  
8
8
7
tIH  
ns  
tIPW  
tMRD  
tRAS  
ns  
tCK  
ns  
40  
120000  
40  
120000  
Active to Active/Auto refresh command  
period  
tRC  
55  
60  
ns  
Preliminary Data Sheet E0601E10 (Ver. 1.0)  
12  
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