EBD25UC8AMFA-5
Pin Capacitance (TA = 25°C, VDD = 2.6V 0.1V)
Parameter
Symbol
CI1
Pins
max.
75
Unit
pF
Notes
Address, /RAS, /CAS, /WE,
/CS, CKE
Input capacitance
Input capacitance
CI2
CK, /CK
60
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
10
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.6V 0.1V, VSS = 0V)
(DDR SDRAM Component Specification)
Parameter
Symbol
tCK
min.
5
max.
8
Unit
Notes
10
Clock cycle time
CK high-level width
CK low-level width
ns
tCH
0.45
0.45
0.55
0.55
tCK
tCK
tCL
min
(tCH, tCL)
CK half period
tHP
—
tCK
DQ output access time from CK, /CK
DQS output access time from CK, /CK
DQS to DQ skew
tAC
–0.7
–0.6
—
0.7
0.6
0.4
—
ns
2, 11
2, 11
3
tDQSCK
tDQSQ
tQH
ns
ns
DQ/DQS output hold time from DQS
Data hold skew factor
tHP – tQHS
—
ns
tQHS
tHZ
0.5
0.7
0.7
1.1
0.6
—
ns
Data-out high-impedance time from CK, /CK
Data-out low-impedance time from CK, /CK
Read preamble
—
ns
5, 11
6, 11
tLZ
–0.7
0.9
0.4
0.4
0.4
1.75
0
ns
tRPRE
tRPST
tDS
tCK
tCK
ns
Read postamble
DQ and DM input setup time
8
8
7
DQ and DM input hold time
tDH
—
ns
DQ and DM input pulse width
Write preamble setup time
tDIPW
tWPRES
tWPRE
tWPST
tDQSS
tDSS
tDSH
tDQSH
tDQSL
tIS
—
ns
—
ns
Write preamble
0.25
0.4
0.72
0.2
0.2
0.35
0.35
0.6
0.6
2.2
2
—
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
Write postamble
0.6
1.25
—
9
Write command to first DQS latching transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
—
—
DQS input low pulse width
—
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command period
Auto refresh to Active/Auto refresh command period
Active to Read/Write delay
—
8
8
7
tIH
—
ns
tIPW
—
ns
tMRD
tRAS
tRC
—
tCK
ns
40
120000
—
55
ns
tRFC
tRCD
tRP
70
—
ns
15
—
ns
Precharge to active command period
15
—
ns
Preliminary Data Sheet E0453E10 (Ver. 1.0)
11
ELPIDA [ ELPIDA MEMORY ]
