EBD10RD4ABFA
Pin Capacitance (TA = +25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
12
Unit
pF
Notes
1, 3
Address, /RAS, /CAS, /WE,
/CS, CKE
CK, /CK
Input capacitance
Input capacitance
CI2
20
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
15
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol min.
max
12
min.
max
12
min.
max
12
Unit Notes
Clock cycle time
(CL = 2)
tCK
7.5
7.5
10
ns
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
0.45
0.55
0.55
0.45
0.55
0.55
tCK
tCK
0.45
0.45
0.45
min
min
min
CK half period
tHP
tAC
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from
CK, /CK
–0.7
0.7
–0.75
0.75
–0.75
0.75
2, 11
DQS output access time from CK,
tDQSCK –0.6
0.6
–0.75
—
0.75
0.5
–0.75
—
0.75
0.5
ns
ns
ns
ns
ns
2, 11
3
/CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data hold skew factor
Data-out high-impedance time
from CK, /CK
tDQSQ
tQH
—
0.45
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
tQHS
tHZ
—
0.55
—
0.75
—
0.75
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
tLZ
–0.7
–0.75
–0.75
ns
Read preamble
tRPRE 0.9
tRPST 0.4
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
tDS
0.45
8
8
7
tDH
0.45
1.75
—
—
—
ns
tDIPW
—
—
—
ns
tWPRES 0
—
—
—
ns
tWPRE 0.25
tWPST 0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from
CK
tDQSS 0.75
1.25
—
0.75
0.2
1.25
—
0.75
0.2
1.25
—
tCK
tCK
tCK
0.2
0.2
tDSH
—
0.2
—
0.2
—
DQS input high pulse width
tDQSH 0.35
tDQSL 0.35
—
—
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
DQS input low pulse width
Address and control input setup
time
tIS
0.75
—
0.9
—
0.9
—
ns
8
Preliminary Data Sheet E0274E40 (Ver. 4.0)
12
ELPIDA [ ELPIDA MEMORY ]
