PRELIMINARY DATA SHEET
128MB DDR SDRAM S.O. DIMM
EBD13UB6ALS (16M words × 64 bits, 2 Banks)
Description
Features
The EBD13UB6ALS is 16M words × 64 bits, 2 banks
Double Data Rate (DDR) SDRAM module, mounted 8
pieces of 128M bits DDR SDRAM (EDD1216ALTA)
sealed in TSOP package. Read and write operations
are performed at the cross points of the CLK and the
/CLK. This high-speed data transfer is realized by the
2 bits prefetch-pipelined architecture. Data strobe
(DQS) both for read and write are available for high
speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 200-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
• 200-pin socket type package (dual lead out)
Outline: 67.6mm (Length) × 31.75mm (Height) ×
3.80mm (Thickness)
Lead pitch: 0.6mm
• 2.5V power supply
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 133MHz/100MHz (max.)
• Data inputs and outputs are synchronized with DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
Burst read stop capability
• Programmable burst sequence
Sequential
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Interleave
• Start addressing capability
Even and Odd
• Programmable /CAS latency (CL): 2, 2.5
• 4096 refresh cycles: 15.6µs (4096/64ms)
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0219E10 (Ver. 1.0)
Date Published October 2001 (K)
Printed in Japan
URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
ELPIDA [ ELPIDA MEMORY ]
