EBD13UB6ALS
Byte No. Function described
95 to 98 Module serial number
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
99 to 127 Manufacture specific data
Block Diagram
/CS1
/CS0
R
R
S
S
/CS
/CS
/CS
/CS
DQS0
DQS4
LDQS
LDM
LDQS
LDM
LDQS
LDM
LDQS
LDM
R
R
R
S
R
S
R
S
S
DM0
DM4
8
8
8
8
S
I/O0 to I/O7
UDQS
I/O0 to I/O7
UDQS
DQ0 to DQ7
DQ32 to DQ39
I/O0 to I/O7
I/O0 to I/O7
R
S
D2
D6
DQS1
DQS5
UDQS
UDQS
D0
D4
R
R
R
R
S
S
UDM
UDM
DM1
DM5
UDM
UDM
S
S
DQ8 to DQ15
I/O8 to I/O15
I/O8 to I/O15
DQ40 to DQ47
I/O8 to I/O15
I/O8 to I/O15
R
S
R
S
/CS
/CS
/CS
/CS
DQS2
DQS6
LDQS
LDQS
LDQS
LDQS
R
R
R
R
R
S
S
S
S
LDM
LDM
DM2
DM6
LDM
LDM
8
8
8
8
S
I/O0 to I/O7
UDQS
I/O0 to I/O7
UDQS
DQ16 to DQ23
DQ48 to DQ55
I/O0 to I/O7
I/O0 to I/O7
R
S
D3
D7
DQS3
DQS7
UDQS
UDQS
D1
D5
R
R
R
R
S
S
UDM
UDM
DM3
DM7
UDM
UDM
S
S
DQ24 to DQ31
I/O8 to I/O15
I/O8 to I/O15
DQ56 to DQ63
I/O8 to I/O15
I/O8 to I/O15
* D0 to D7 : EDD1216ALTA
U0 : 2k bits EEPROM
Rs : 22Ω
Serial PD
BA0 to BA1
A0 to A11
/RAS
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D3)
SDRAMs (D4 to D7)
SCL
SA0
SA1
SA2
SCL
SDA
SDA
A0
A1
A2
U0
/CAS
/WE
CKE0
CKE1
CLK0
SDRAMs (D0, D1, D4, D5)
SDRAMs (D2, D3, D6, D7)
VDDSPD
VREF
SPD
SDRAMs (D0 to D7)
/CLK0
CLK1
/CLK1
VDD
SDRAMs (D0 to D7), VDD and VDDQ
SDRAMs (D0 to D7), SPD
CLK2
10 pF
/CLK2
VSS
Notes :
VDDID
Open
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
Strap in (closed): VDD ≠ VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Preliminary Data Sheet E0219E10 (Ver. 1.0)
7
ELPIDA [ ELPIDA MEMORY ]
