EBD11UD8ABFB
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Device Specification)
-6B
-7A
-7B
Parameter
Clock cycle time
(CL = 2)
Symbol min.
max.
12
min.
max
12
min.
max
12
Unit Notes
tCK
7.5
7.5
10
ns
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
0.45
0.55
0.55
0.45
0.55
0.55
tCK
tCK
0.45
0.45
0.45
min
min
min
CK half period
tHP
tAC
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from
CK, /CK
–0.7
0.7
–0.75
0.75
–0.75
0.75
2, 11
DQS output access time
tDQSCK –0.6
0.6
–0.75
—
0.75
0.5
–0.75
—
0.75
0.5
ns
ns
ns
ns
ns
2, 11
3
from CK, /CK
DQS to DQ skew
DQ/DQS output hold time
from DQS
Data hold skew factor
Data-out high-impedance
time from CK, /CK
tDQSQ
tQH
—
0.45
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
tQHS
tHZ
—
0.55
—
0.75
—
0.75
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
5, 11
6, 11
Data-out low-impedance
time from CK, /CK
tLZ
–0.7
–0.75
–0.75
ns
Read preamble
tRPRE
tRPST
0.9
1.1
0.6
—
0.9
0.4
0.5
0.5
1.1
0.6
—
0.9
0.4
0.5
0.5
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time tDS
0.45
0.45
8
8
DQ and DM input hold time tDH
DQ and DM input pulse
width
—
—
—
ns
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time tWPRES
0
—
0
—
0
—
ns
Write preamble
tWPRE
tWPST
0.25
0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
DQS falling edge to CK
setup time
DQS falling edge hold time
from CK
tDQSS
tDSS
0.75
0.2
1.25
—
0.75
0.2
1.25
—
0.75
0.2
1.25
—
tCK
tCK
tCK
tDSH
0.2
—
0.2
—
0.2
—
DQS input high pulse width tDQSH
0.35
0.35
—
—
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
DQS input low pulse width tDQSL
Address and control input
tIS
0.75
0.75
2.2
2
—
0.9
0.9
2.2
2
—
0.9
0.9
2.2
2
—
ns
ns
ns
tCK
ns
ns
8
8
7
setup time
Address and control input
hold time
tIH
—
—
—
Address and control input
tIPW
—
—
—
pulse width
Mode register set command
cycle time
tMRD
—
—
—
Active to Precharge
tRAS
42
120000
—
45
120000
—
45
120000
—
command period
Active to Active/Auto refresh
tRC
60
67.5
67.5
command period
Preliminary Data Sheet E0296E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
