EBD10RD4ADFA-E
Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle
6ns
7.5ns
min.
tCK
Parameter
Symbol
tWPD
min.
max.
—
max.
—
Unit
tCK
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write command delay
(CL = 3)
4 + BL/2
BL/2
3 + BL/2
BL/2
tRPD
—
—
—
—
—
tCK
tCK
tWRD
2 + BL/2
2 + BL/2
tBSTW
tBSTW
tBSTZ
tBSTZ
—
3
2
—
—
3
tCK
tCK
tCK
tCK
(CL = 3.5)
Burst stop command to DQ High-Z
(CL = 3)
3
—
3.5
—
3
(CL = 3.5)
3.5
3.5
3.5
Read command to write command delay
(to output all data)
(CL = 3)
tRWD
—
—
2 + BL/2
—
tCK
(CL = 3.5)
Pre-charge command to High-Z
(CL = 3)
tRWD
tHZP
3 + BL/2
—
3 + BL/2
3
—
3
tCK
tCK
—
(CL = 3.5)
tHZP
tWCD
tWR
3.5
2
3.5
—
3.5
2
3.5
2
tCK
tCK
tCK
Write command to data in latency
Write recovery
2
—
1
—
Register set command to active or register
set command
tMRD
2
—
2
—
tCK
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
tSNR
12
200
1
—
—
1
10
200
1
—
—
1
tCK
tCK
tCK
tCK
tSRD
tPDEN
tPDEX
Power down exit to command input
1
—
1
—
Data Sheet E0607E10 (Ver. 1.0)
14
ELPIDA [ ELPIDA MEMORY ]
