EBD10RD4ADFA-E
-6B
-7A
-7B
Parameter
Symbol min.
max
—
min.
max
—
min.
0.9
max
—
Unit Notes
Address and control input hold
time
Address and control input pulse
width
Mode register set command cycle
time
Active to Precharge command
period
tIH
0.75
2.2
2
0.9
2.2
2
ns
8
7
tIPW
tMRD
tRAS
tRC
—
—
2.2
2
—
ns
—
—
—
tCK
ns
42
120000
—
45
65
120000
—
45
65
120000
—
Active to Active/Auto refresh
command period
60
ns
Auto refresh to Active/Auto refresh
tRFC
tRCD
tRP
72
18
18
—
—
—
75
20
20
—
—
—
75
20
20
—
—
—
ns
ns
ns
command period
Active to Read/Write delay
Precharge to active command
period
Active to auto precharge delay
Active to active command period
Write recovery time
tRAP
tRRD
tWR
tRCD min.
—
—
—
tRCD min.
—
—
—
tRCD min.
—
—
—
ns
ns
ns
12
15
15
15
15
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
—
tCK 13
Internal write to Read command
delay
Average periodic refresh interval
tWTR
tREF
1
—
1
—
1
—
tCK
µs
—
7.8
—
7.8
—
7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Data Sheet E0607E10 (Ver. 1.0)
13
ELPIDA [ ELPIDA MEMORY ]
