EDJ2108EEBG, EDJ2116EEBG
Pin Configurations (× 16 configuration)
/xxx indicates active low signal.
96-ball FBGA
3
1
2
7
8
9
A
VDDQ DQU5 DQU7
VSSQ VDD VSS
DQU4 VDDQ VSS
B
C
D
E
/DQSU DQU6 VSSQ
DQSU DQU2 VDDQ
DQU0 VSSQ VDD
VDDQ
DQU3 DQU1
VSSQ VDDQ DMU
VSS VSSQ DQL0
DML VSSQ VDDQ
DQL1 DQL3 VSSQ
F
G
H
J
VDDQ DQL2 DQSL
VSSQ DQL6 /DQSL
VREFDQ VDDQ DQL4
VDD
VSS VSSQ
DQL7 DQL5 VDDQ
NC
VSS /RAS
CK
VSS
VDD
NC
CKE
NC
K
L
/CK
ODT VDD /CAS
NC
/CS
/WE
BA2
A10(AP) ZQ
M
N
P
R
T
VSS
BA0
NC VREFCA VSS
VDD
VSS
VDD
A3
A5
A7
A0
A2
A9
A12(/BC) BA1
VDD
VSS
VDD
VSS
A1
A11
NC
A4
A6
A8
VSS /RESET A13
(Top view)
Pin name
Function
Address inputs
Pin name
Function
A0 to A13*2
BA0 to BA2*2
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*2
Active low asynchronous reset
Bank select
VDD
VSS
Supply voltage for internal circuit
Ground for internal circuit
DQU0 to DQU7
DQL0 to DQL7
Data input/output
DQSU, /DQSU
DQSL, /DQSL
Differential data strobe
VDDQ
Supply voltage for DQ circuit
/CS*2
/RAS, /CAS, /WE*2
CKE*2
Chip select
VSSQ
VREFDQ
VREFCA
ZQ
Ground for DQ circuit
Command input
Clock enable
Reference voltage for DQ
Reference voltage for CA
Reference pin for ZQ calibration
No connection
CK, /CK
Differential clock input
Write data mask
ODT control
DMU, DML
ODT*2
NC*1
Notes: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1750E31 (Ver. 3.1)
4
ELPIDA [ ELPIDA MEMORY ]
