GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
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Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must
be set to enable for the Quad I/O Fast read command.
Rev.1.0
50 - 20
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