GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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Figure 40. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
LSB
High-Z
SO
Figure 41. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure 42. Hold Timing
CS#
tCHHL
tHLCH
tHHCH
tHHQX
SCLK
tCHHH
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
Rev.1.0
59 - 54