GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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7.35. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return
to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write
Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read
Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset
(99H)”command sequence as follow: CS# goes low → Sending Enable Reset command → CS# goes high
→ CS# goes low → Sending Reset command → CS# goes high. Once the Reset command is accepted by the
device, the device will take approximately tRST=30µs to reset. During this period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit
in Status Register before issuing the Reset command sequence.
Figure 37. Enable Reset and Reset command Sequence Diagram
Figure 37a. Enable Reset and Reset command Sequence Diagram (QPI)
CS#
0
0
1
1
SCLK
Command
66H
Command
99H
IO0
IO1
IO2
IO3
Rev.1.0
59 - 49
ELM [ ELM ELECTRONICS ]
