DESIGN CONSIDERATIONS
TEST CONFIGURATIONS
Input Source Impedance
TO OSCILLOSCOPE
L
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. The models using 4x47 uF very low ESR
VI(+)
VI(-)
4×47uF
BATTERY
ceramic
ceramic
capacitors
(MURATA
P/N:
GRM32ER61C476ME15L, 47uF/16V or equivalent) for
example.
The input capacitance should be able to handle an AC
ripple current of at least:
Note: Input reflected-ripple current is measured with a
simulated source inductance. Current is
measured at the input of the module.
Vout
Vin
Vout
Vin
Irms = Iout
1 −
Arms
Figure 25: Input reflected-ripple test setup
450
400
350
300
250
200
150
100
50
COPPER STRIP
Vo
Resistive
Load
1uF
100uF
ceramic ceramic
SCOPE
GND
Ceramic
0
0
1
2
3
4
5
6
Output Voltage (Vdc)
Note: Use a 100µF and 1µF ceramic capacitor. Scope
measurement should be made using a BNC
connector.
Figure 28: Input ripple voltage vs. output models, Io = 20A
(Cin = 4x22uF ceramic capacitors at the input)
Figure 26: Peak-peak output noise and startup transient
measurement test setup
CONTACT AND
DISTRIBUTION LOSSES
VI
Vo
I
Io
LOAD
SUPPLY
GND
CONTACT RESISTANCE
Figure 27: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module
terminals. When the module is not soldered (via
socket), place Kelvin connections at module
terminals to avoid measurement errors due to
contact resistance.
Vo× Io
η = (
)×100 %
Vi × Ii
DS_DNL10SMD_07182012
7
DELTA [ DELTA ELECTRONICS, INC. ]
