FEATURES DESCRIPTIONS (CON.)
Voltage Margining
Table 1 provides Rtrim values required for some common
output voltages, By using a 0.5% tolerance trim resistor,
set point tolerance of ±1.5% can be achieved as specified
in the electrical specification.
Output voltage margining can be implemented in the DCM
modules by connecting a resistor, R margin-up, from the Trim
pin to the ground pin for margining-up the output voltage
and by connecting a resistor, Rmargin-down, from the Trim pin
to the output pin for margining-down. Figure 33 shows the
circuit configuration for output voltage margining. If unused,
leave the trim pin unconnected. A calculation tool is
available from the evaluation procedure which computes
the values of Rmargin-up and Rmargin-down for a specific output
voltage and margin percentage.
Table 1
Open
3K
0.6V
1V
2K
1.2V
1.5V
1.8V
2.5V
3.3V
1.333K
1K
0.632K
0.444K
Vo
Vin
Rmargin-down
Q1
Certain restrictions apply on the output voltage set point
depending on the input voltage. These are shown in the
Output Voltage vs. Input Voltage Set Point Area plot in
Figure 32. The Upper Limit curve shows that for output
voltages of 3.3V and lower, the input voltage must be
lower than the maximum of 5.5V. The Lower Limit curve
shows that for output voltages of 1.8V and higher, the input
voltage needs to be larger than the minimum of 2.4V.
Trim
GND
On/Off
Rmargin-up
Q2
Rtrim
Figure 33: Circuit configuration for output voltage margining
Output Voltage Sequencing
The DCM 12V 12A modules include a sequencing feature,
EZ-SEQUENCE that enables users to implement various
types of output voltage sequencing in their applications.
This is accomplished via an additional sequencing pin.
When not using the sequencing feature, either tie the SEQ
pin to VIN or leave it unconnected.
When an analog voltage is applied to the SEQ pin, the
output voltage tracks this voltage until the output reaches
the set-point voltage. The final value of the SEQ voltage
must be set higher than the set-point voltage of the module.
The output voltage follows the voltage on the SEQ pin on a
one-to-one basis. By connecting multiple modules together,
multiple modules can track their output voltages to the
voltage applied on the SEQ pin.
Figure 32: Output Voltage vs. Input Voltage Set Point Area plot
showing limits where the output voltage can be set for different
input voltages.
DS_ DCM04S0A0S12PFA_10022013
E-mail: DCDC@delta.com.tw
http://www.deltaww.com/dcdc
P9
DELTA [ DELTA ELECTRONICS, INC. ]
