XBee®/XBee‐PRO® ZB SMT RF Modules
Application Interrupt Vector table and Linker Command File
Since the bootloader flash region is read-only, the interrupt vector table is redirected to the region
0xF1C0 to 0xF1FD so that application developers can use hardware interrupts. Note that in order for
Application interrupts to function properly, the Application's linker command file (*.prm extension)
must be modified appropriately to allow the linker to place the developers code in the correct place in
memory. For example, the developer desires to use the serial communications port SCI1 receive
interrupt. The developer would add the following line to the Codewarrior linker command file for the
project:
VECTOR ADDRESS 0x0000F1E0 vSci1Rx
This will inform the linker that the interrupt function "vSci1Rx()" should be placed at address
0x0000F1E0. Next, the developer should add a file to their project "vector_table.c" that creates an
array of function pointers to the ISR routines used by the application.
extern void _Startup(void);/* _Startup located in Start08.c */
extern void vSci1Rx(void);/* sci1 rx isr */
extern short iWriteToSci1(unsigned char *);
void vDummyIsr(void);
#pragma CONST_SEG VECTORS
void (* const vector_table[])(void) = /* Relocated Interrupt vector table */{
vDummyIsr,/* Int.no. 0 Vtpm3ovf (at F1C0)Unassigned */
vDummyIsr, /* Int.no. 1 Vtpm3ch5 (at F1C2) Unassigned */
vDummyIsr, /* Int.no. 2 Vtpm3ch4 (at F1C4) Unassigned */
vDummyIsr, /* Int.no. 3 Vtpm3ch3 (at F1C6) Unassigned */
vDummyIsr, /* Int.no. 4 Vtpm3ch2 (at F1C8) Unassigned */
vDummyIsr, /* Int.no. 5 Vtpm3ch1 (at F1CA) Unassigned */
vDummyIsr, /* Int.no. 6 Vtpm3ch0 (at F1CC) Unassigned */
vDummyIsr, /* Int.no. 7 Vrtc (at F1CE)
vDummyIsr, /* Int.no. 8 Vsci2tx (at F1D0)
vDummyIsr, /* Int.no. 9 Vsci2rx (at F1D2)
Unassigned */
Unassigned */
Unassigned */
vDummyIsr, /* Int.no. 10 Vsci2err (at F1D4) Unassigned */
vDummyIsr, /* Int.no. 11 Vacmpx (at F1D6)
vDummyIsr, /* Int.no. 12 Vadc (at F1D8)
Unassigned */
Unassigned */
vDummyIsr, /* Int.no. 13 Vkeyboard (at F1DA) Unassigned */
vDummyIsr, /* Int.no. 14 Viic (at F1DC)
vDummyIsr, /* Int.no. 15 Vsci1tx (at F1DE)
vSci1Rx, /* Int.no. 16 Vsci1rx (at F1E0)
Unassigned */
Unassigned */
SCI1RX */
vDummyIsr, /* Int.no. 17 Vsci1err (at F1E2) Unassigned */
vDummyIsr, /* Int.no. 18 Vspi (at F1E4) Unassigned */
vDummyIsr, /* Int.no. 19 VReserved12 (at F1E6) Unassigned */
vDummyIsr, /* Int.no. 20 Vtpm2ovf (at F1E8) Unassigned */
vDummyIsr, /* Int.no. 21 Vtpm2ch2 (at F1EA) Unassigned */
vDummyIsr, /* Int.no. 22 Vtpm2ch1 (at F1EC) Unassigned */
vDummyIsr, /* Int.no. 23 Vtpm2ch0 (at F1EE) Unassigned */
vDummyIsr, /* Int.no. 24 Vtpm1ovf (at F1F0) Unassigned */
vDummyIsr, /* Int.no. 25 Vtpm1ch2 (at F1F2) Unassigned */
vDummyIsr, /* Int.no. 26 Vtpm1ch1 (at F1F4) Unassigned */
vDummyIsr, /* Int.no. 27 Vtpm1ch0 (at F1F6) Unassigned */
© 2010 Digi International, Inc.
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DCD [ DIGITAL CORE DESIGN ]
