DR805x Instructions set details
- 21 -
3.5.3. ANL A, @RI
Operation: (PC) ← (PC) + 1
(A) ← (A) and ((Ri))
Bytes:
Cycles:
1
3
Encoding:
0
1
0
1
0
1
1
0
1
1
i
3.5.4. ANL A, #DATA
Operation: (PC) ← (PC) + 2
(A) ← (A) and #data
Bytes:
Cycles:
2
2
Encoding:
0
1
0
1
0
1
0
0
1
immediate data
3.5.5. ANL DIRECT, A
Operation: (PC) ← (PC) + 2
(direct) ← (direct) and (A)
Bytes:
Cycles:
2
4
Encoding:
0
1
0
1
0
0
direct address
3.5.6. ANL DIRECT, #DATA
Operation: (PC) ← (PC) + 3
(direct) ← (direct) and #data
Bytes:
Cycles:
3
4
Encoding:
0
1
0
1
0
0
direct address
immediate data
Instruction:
ANL C, <src-bit>
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