DR805x Instructions set details
- 18 -
3.3.3. ADDC A, @RI
Operation:
(PC) ← (PC) + 1
(A) ← (A) + (C) + ((Ri))
Bytes:
Cycles:
1
3
Encoding:
0
0
1
1
0
1
1
i
3.3.4. ADDC A, #DATA
Operation:
(PC) ← (PC) + 2
(A) ← (A) + (C) + #data
Bytes:
Cycles:
2
2
Encoding:
0
0
1
1
0
1
0
0
immediate data
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.