SYMBOL
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
BLOCK DIAGRAM
Opcode
decoder
prgromdata(7:0) prgaddr(15:0)
prgramdata(7:0) prgdatao(7:0)
prgramwr
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
Program
memory
interface
External
memory
interface
Interrupt
controller
int0
int1
Control
Unit
ramdatai(7:0)
Power
Management
Unit
stop
pmm
Internal data
memory
interface
DoCD™
Debug Unit
docddatai
docddatao
docdclk
sfrdatai(7:0)
User SFR’s
interface
ALU
PINS DESCRIPTION
PIN
clk
reset
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
iprgramsize[2:0]
iprgromsize[2:0]
prgramdata[7:0]
prgromdata[7:0]
xdatai[7:0]
ready
ramdatai[7:0]
sfrdatai[7:0]
int0
int1
docddatai
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
prgaddr[15:0]
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
DESCRIPTION
Global clock
Global reset
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from external memories
External memory data ready
Data bus from internal data memory
Data bus from user SFR’s
External interrupt 0
External interrupt 1
DoCD™ data input
reset
clk
output Port 0 output
output Port 1 output
output Port 2 output
output Port 3 output
output Internal program memory address bus
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Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
