B L O C K D I A G R A M
Figure below shows the DMAC IP Core block
diagram.
P E R F O R M A N C E
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
TX RAM pins
txclk
crs
col
txen
txer
TX RAM interface
Transmit
module
docdbusctrl
clk
rst
rdcs
wrcs
rd
Fmax [MHz]
Speed
grade
Device
Logic Cells
txdata(3:0)
clk / rxclk / txclk
mdi
mdc
mdo
mdoe
STRATIX II
CYCLONE II
STRATIX GX
STRATIX
-3
-6
-5
-5
-6
-7
-7
-1
-1
967 + 4 kB RAM 211 / 200 / 175
1222 + 4 kB RAM 150 / 156 / 152
1255 + 4 kB RAM 152 / 156 / 138
1255 + 4 kB RAM 162 / 147 / 137
1254 + 4 kB RAM 148 / 133 / 133
1622 + 4 kB RAM 145 / 106 / 111
1622 + 4 kB RAM 127 / 118 / 117
1622 + 4 kB RAM 108 / 99 / 111
Synchronization
logic
Control &
I/O logic
STA
wr
be(3:0)
rdaddr(4:0)
wraddr(4:0)
datai(31:0)
irq
rxclk
rxdv
rxer
Receive
module
CYCLONE
APEX II
APEX20KC
APEX20KE
APEX20K
RX FIFO
rxdata(3:0)
datao(31:0)
RX RAM pins
1622 + 4 kB RAM
86 / 87 / 88
Core performance in ALTERA® devices
Transmit module – Performs transmit man-
agement functions, sends frames to Ethernet
medium.
Receive module – is responsible for receiv-
ing frames from the Ethernet. Provides nec-
essary functions for frame decapsulation,
CRC checking, address recognizing and error
detection.
Synchronization logic – There are 3 clock
domains in the DMAC core. This module per-
forms synchronization between these.
TX RAM / RX FIFO RAM interfaces – Inter-
faces to external dual port memories used by
the DMAC core to store received and trans-
mitted frames.
Control and I/O logic – This module pro-
vides interface to CPU/BUS. It exchanges
data and control logic with transmit and re-
ceive modules, thus controls these to perform
transmit and receive operations.
STA – Station Management entity provides
capability to communicate with PHY by sim-
ple serial management interface.
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