P I N S D E S C R I P T I O N
D E L I V E R A B L E S
♦ Source code:
PIN
TYPE
DESCRIPTION
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
clk
input Global clock
rst
input Global reset
rdcs
wrcs
rd
input Read chip select
input Write chip select
input Read data strobe
◊ Active-HDL automatic simulation mac-
ros
wr
input Write data strobe
rdaddr(4:0)
wraddr(4:0)
be(3:0) 2
datai(31:0)1
qmr(31:0)
qmt(31:0)
rxdata(3:0)
rxdv
input Host read address bus
input Host write address bus
input Host byte enable
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
input Host output data bus
input RX DPRAM data output
input TX DPRAM data output
input Ethernet receive data
input Ethernet receive data valid
input Ethernet receive error
input Ethernet receive clock
input Ethernet transmit clock
input Ethernet carrier sense
input Ethernet collision detection
input Management data input
input DoCD debugger input
output Host input data bus
output Interrupt signal
♦ Example application
♦ Technical support
rxer
◊ IP Core implementation support
◊ 3 months maintenance
rxclk
●
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
txclk
crs
●
●
col
mdi
docdbusctrl
datao(31:0)1
irq
S Y M B O L
rst
rdcs
wrcs
dmt(31:0)
waddrmt(8:0)
raddrmt(8:0)
enrmt
dmr(31:0)
waddrmr(8:0)
raddrmr(8:0)
enrmr
output RX DPRAM data input
output RX DPRAM write address
output RX DPRAM read address
output RX DPRAM read enable
output RX DPRAM write enable
output TX DPRAM data input
output TX DPRAM write address
output TX DPRAM read address
output TX DPRAM read enable
output TX DPRAM write enable
output Ethernet transmit error
output Ethernet transmit enable
output Ethernet transmit data
output Management clock
output Management data output
output Management data output enable
input Global clock
enwmt
qmt(31:0)
enwmr
dmt(31:0)
waddrmt(8:0)
raddrmt(8:0)
enrmt
rd
wr
be(3:0)2
datai(31:0)1
rdaddr(4:0)
wraddr(4:0)
clk
datao(31:0)1
irq
enwmt
txer
dmr(31:0)
waddrmr(8:0)
raddrmr(8:0)
enrmr
qmr(31:0)
txen
rxdata(3:0)
rxdv
rxer
txdata(3:0)
mdc
enwmr
rxclk
mdo
crs
col
txclk
txdata(3:0)
txen
mdoe
clk
txer
rst
input Global reset
rdcs
input Read chip select
mdi
mdc
mdo
wrcs
input Write chip select
mdoe
docdbusctrl
1 – data bus can be configured as 8-, 16- or 32- bit depends
on processor’s bus size
2 – byte enable (be) size is set accordingly to data bus size
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DCD [ DIGITAL CORE DESIGN ]
