LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design
license allows using IP Core in
single FPGA bitstream and ASIC implemen-
tation. It also permits FPGA prototyping be-
fore ASIC production.
Unlimited Designs
license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
Single Design license for
○
VHDL, Verilog source code called HDL
clk
rst
cs
PINS DESCRIPTION
PIN
TYPE
Input
Input
Input
Input
Input
Input
2
DESCRIPTION
Global system clock
Global system reset
Chip select for read/write
Data bus input
Register address to read/write
Data write enable
datai[31:0]
1
addr[4:2]
we
datao[31:0]
1
irq
Output Data bus output
Output Interrupt request indicator
1 – data bus can be configured as 8-, 16- or 32- bit
depends on processor’s bus size
2 – address bus is aligned to work with 8- (3:0), 16-
(3:1) or 32- (4:2) bit processors
BLOCK DIAGRAM
Mantissa –
performs operations on mantissa
part of number. The addition, subtraction,
multiplication, division, square root, compari-
son and conversion operations are executed
in this module. It contains mantissas and
work registers.
CORDIC –
performs trigonometric operations
on input data. The sine, cosine, tangent and
arctangent operations are executed in this
module. It contains three work registers.
datai(31:0)
1
datao(31:0)
1
irq
addr(4:2)
we
cs
2
Source
○
Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○
HDL Source
○
Netlist
●
Upgrade from
○
Netlist to HDL Source
○
Single Design to Unlimited Designs
SYMBOL
datai(31:0)
1
addr(4:2)
we
2
datao(31:0)
1
Mantissa
Interface
irq
Align
cs
rst
clk
Exponent
Shifter
CORDIC
clk
rst
Control
Unit
Exponent –
performs operations on expo-
nent part of number. The addition, subtrac-
tion, shifting, comparison and conversion
operations are executed in this module. It
contains exponents and work registers.
Align –
performs the numbers analyze
against IEEE-754 standard compliance. In-
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
