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SLLS763B – JANUARY 2007 – REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TTL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
C
I
V
I
V
ID(th)
t
r
/t
f
C
I
R
I
t
su
t
h
T
(duty)
V
OD
V
OS
V
OD
V
OS
I
(SP)
, I
(SN)
,
I
(SPN)
I
off
t
(cq_min)
t
(cq_max)
t
r
/t
f
High-level input voltage
Low-level input voltage
Input high current
Input low current
High-level output voltage
Low-level output voltage
Input capacitance
Input voltage
Input differential threshold voltage
See
Input transition time
Input capacitance
Input differential impedance
Input setup time requirement
Input hold time requirement
Input clock duty cycle
Output differential voltage
Output common mode voltage
Change VOD between 1 and 0
Change VOS between 1 and 0
Output short circuit current
Power-off current
Clock-output time
Output transition time
Output clock duty cycle
Data output to FRAME_SYNC delay
Outputs shorted to ground or shorted together
V
DD
= 0 V
See
20% to 80%
100
45%
4
R
L
= 100
±1%
On-chip termination
See
See
80
300
300
40%
300
1070
60%
800
1375
25
25
24
10
100
100
300
55%
7 Bit times
mA
µA
ps
ps
mV
100
Assumes 60% / 40% duty cycle
Assumes 55% / 45% duty cycle
20% to 80%
825
250
200
375
3
120
V
DD
= MAX, V
IN
= 2 V
V
DD
= MAX, V
IN
=0.4 V
I
OH
= –1 mA
I
OH
= 1 mA
–40
2.10
2.3
0.25
0.5
4
1575
2
3.6
0.80
40
V
V
µA
µA
V
V
pF
mV
mV
ps
pF
Ω
ps
ps
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS INPUT SIGNALS
LVDS OUTPUT SIGNALS
(OC-48 = 622.08 MHz, Clock Rates With t
r
/t
f
≤
500 ps)
250
200
LVDS V
ID
- Input - mV
150
100
50
0
40
42
44
46 48 50 52 54
Input Duty-Cycle - %
56
58
60
Figure 5. LVDS Differential Input Voltage vs Input Duty Cycle
13
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