DM9161C
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Content
1. GENERAL DESCRIPTION.................................................................................................................................................................. 4
2. FEATURES ............................................................................................................................................................................................ 4
3. BLOCK DIAGRAM ............................................................................................................................................................................... 5
4. PIN CONFIGURATION: ....................................................................................................................................................................... 6
4.1 48-
PIN
LQFP...................................................................................................................................................................................... 6
5. PIN DESCRIPTION............................................................................................................................................................................... 7
5.1 N
ORMAL
MII I
NTERFACE
.................................................................................................................................................................... 7
5.2 M
EDIA
I
NTERFACE
.............................................................................................................................................................................. 9
5.3 LED I
NTERFACE
................................................................................................................................................................................. 9
5.4 M
ODE
.................................................................................................................................................................................................. 9
5.5 B
IAS AND
C
LOCK
..............................................................................................................................................................................12
5.6 P
OWER
.............................................................................................................................................................................................12
5.7 T
ABLE A
(M
EDIA
T
YPE
S
ELECTION
)..................................................................................................................................................12
5.8 P
IN
M
APS OF
N
ORMAL
MII, R
EDUCED
MII,
AND
10B
ASE
-T GPSI (7-W
IRED
) M
ODE
.....................................................................12
6. LED CONFIGURATION.....................................................................................................................................................................14
6.1 LED F
UNCTION
D
ESCRIPTION
.........................................................................................................................................................15
7. FUNCTIONAL DESCRIPTION .........................................................................................................................................................16
7.1 MII I
NTERFACE
..................................................................................................................................................................................16
7.2 100B
ASE
-TX O
PERATION
................................................................................................................................................................18
8. MII REGISTER DESCRIPTION.........................................................................................................................................................25
8.1 B
ASIC
M
ODE
C
ONTROL
R
EGISTER
(BMCR) - 00............................................................................................................................26
8.2 B
ASIC
M
ODE
S
TATUS
R
EGISTER
(BMSR) - 01...............................................................................................................................27
8.3 PHY ID I
DENTIFIER
R
EGISTER
#1 (PHYID1) - 02...........................................................................................................................28
8.4 PHY ID I
DENTIFIER
R
EGISTER
#2 (PHYID2) - 03...........................................................................................................................28
8.5 A
UTO
-
NEGOTIATION
A
DVERTISEMENT
R
EGISTER
(ANAR) - 04......................................................................................................29
8.6 A
UTO
-
NEGOTIATION
L
INK
P
ARTNER
A
BILITY
R
EGISTER
(ANLPAR) – 05.......................................................................................30
8.7 A
UTO
-
NEGOTIATION
E
XPANSION
R
EGISTER
(ANER) - 06 ..............................................................................................................31
8.8 DAVICOM S
PECIFIED
C
ONFIGURATION
R
EGISTER
(DSCR) - 16..................................................................................................31
8.9 DAVICOM S
PECIFIED
C
ONFIGURATION AND
S
TATUS
R
EGISTER
(DSCSR) - 17 .........................................................................33
8.10 10BASE-T C
ONFIGURATION
/S
TATUS
(10BTCSR) - 18..............................................................................................................34
8.12 (S
PECIFIED CONFIG
) R
EGISTER
– 20 .............................................................................................................................................35
8.13 DAVICOM S
PECIFIED
I
NTERRUPT
R
EGISTER
– 21......................................................................................................................36
8.14 DAVICOM S
PECIFIED
R
ECEIVE
E
RROR
C
OUNTER
R
EGISTER
(RECR) – 22.............................................................................36
8.15 DAVICOM S
PECIFIED
D
ISCONNECT
C
OUNTER
R
EGISTER
(DISCR) – 23..................................................................................37
8.16 DAVICOM H
ARDWARE
R
ESET
L
ATCH
S
TATE
R
EGISTER
(RLSR) – 24......................................................................................38
8.17 P
OWER
S
AVING
C
ONTROL
R
EGISTER
(PSCR) – 29 ....................................................................................................................38
9. DC AND AC ELECTRICAL CHARACTERISTICS .......................................................................................................................39
9.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
(25°C)............................................................................................................................................39
9.2 O
PERATING
C
ONDITIONS
.................................................................................................................................................................39
9.3 DC E
LECTRICAL
C
HARACTERISTICS
(DVDD = 3.3V) .....................................................................................................................40
2
Final
Version: DM9161C-DS-F01
October 26, 2011
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
