DM9010
Single Chip Ethernet Controller with General Processor Interface
10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
Symbol
Parameter
Min.
3.0
0
Typ.
Max.
5.0
0.5
Unit
ns
ns
Conditions
tTR/F
tTM
100TX+/- Differential Rise/Fall Time
100TX+/- Differential Rise/Fall Time
Mismatch
-
-
tTDC
tT/T
100TX+/- Differential Output Duty Cycle
Distortion
100TX+/- Differential Output Peak-to-Peak
Jitter
0
0
0
-
-
-
0.5
1.4
5
ns
ns
%
XOST
100TX+/- Differential Voltage Overshoot
10.3.2 Oscillator/Crystal Timing
Symbol
TCKC
TPWH
TPWL
Parameter
Min.
Typ.
Max.
40.002
24
Unit
ns
ns
Conditions
TCKC
39.998
16
16
40
20
20
50ppm
OSC Pulse Width High
OSC Pulse Width Low
24
ns
10.3.3 Processor I/O Read Timing
Symbol
T1
Parameter
System Address(SA) valid to IOR# valid
IOR# width
Min.
0
10
Typ. Max.
Unit
ns
ns
T2
T3
T4
T5
T6
IOR# valid to System Data(SD) valid
IOR# invalid to System Data(SD) bus invalid
IOR# invalid to System Address(SA) invalid
IOR# invalid to next IOR#/IOW# valid
When read DM9010 register
3
3
ns
ns
ns
clk*
0
2
T6
IOR# invalid to next IOR#/IOW# valid
When read DM9010 memory with F0h register
4
1
clk*
clk*
T2+T6 IOR# invalid to next IOR#/IOW# valid
When read DM9010 memory with F2h register
T7
T8
System Address(SA) valid to IO16,IO32 valid
System Address(SA) invalid to IO16, IO32 invalid
3
3
ns
ns
*Note：(the default clk period is 20ns)
Preliminary
50
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
