DM9000B
Ethernet Controller with General Processor Interface
3. Features
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Supports processor interface: byte/word of I/O
command to internal memory data operation
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Integrated 10/100M transceiver With HP
Auto-MDIX
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Supports back pressure mode for half-duplex
IEEE802.3x flow control for full-duplex mode
Supports wakeup frame, link status change and
magic packet events for remote wake up
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Support 100M Fiber interface.
Integrated 16K Byte SRAM
Build in 3.3V to 1.8V regulator
Supports early Transmit
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Supports IP/TCP/UDP checksum generation and
checking
Supports automatically load vendor ID and
product ID from EEPROM
Optional EEPROM configuration
Very low power consumption mode:
– Power reduced mode (cable detection)
– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
Compatible with 3.3V and 5.0V tolerant I/O
DSP architecture PHY Transceiver.
48-pin LQFP, 0.18 um process
Final
Version: DM9000B-13-DS-F03
March 5, 2012
7
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
