DM8203
2-port switch with MII / RMII Interface
9.3 MII Interface
9.3.1 MII data interface
The DM8203 port 2 provides a Media Independent
Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
transmitted from the external device to the DM8203
port 2 MAC.
•
CRS2 (carrier sense) is asserted by the
The MII consists of a nibble wide receive data bus,
a nibble wide transmit data bus, and control signals to
facilitate data transfers between the DM8203 port 2
and external device (a PHY or a MAC in reverse MII).
external device when either the transmit or receive
medium is non-idle, and de-asserted by the external
device when the transmit and receive medium are
idle. The CRS2 can also in output mode when the
DM8203 port 2 is configured to reversed MII mode.
•
TXD2 (transmit data) is a nibble (4 bits) of
•
COL2 (collision detection) is asserted by the
data that are driven by the DM8203 synchronously
with respect to TXC2. For each TXC2 period, which
TXE2 is asserted, TXD2 (3:0) are accepted for
transmission by the external device.
external device, when both the transmit and receive
medium is non-idle, and de-asserted by the external
device when the either transmit or receive medium
are idle. The COL2 can also in output mode when the
DM8203 port 2 is configured to reversed MII mode.
•
TXC2 (transmit clock) from the external
device is a continuous clock that provides the timing
reference for the transfer of the TXE2, TXD2. The
DM8203 can drive 25MHz clock if it is configured to
reversed MII mode.
9.3.2 MII Serial Management
The MII serial management interface consists of a
data interface, basic register set in DM8203 port 0
and 1, and a serial management interface to the
register set. Through this interface it is possible to
control and configure multiple PHY devices, include
internal two ports, get status and error information,
and determine the type and capabilities of the
attached PHY device(s). The DM8203 default is
polling 3 ports basic registers 0, 1, 4, and 5 to get the
link, duplex, and speed status automatically.
Alternatively, the DM8203 can be programmed to
read or write any registers of 3 ports by section
6.8~11 CSR B, C, D, and E.
•
TXE2 (transmit enable) from the DM8203 port
2 MAC indicates that nibbles are being presented on
the MII for transmission to the external device.
•
RXD2 (receive data) is a nibble (4 bits) of data
that are sampled by the DM8203 port 2 MAC
synchronously with respect to RXC2. For each RXC2
period which RXDV2 is asserted, RXD2 (3:0) are
transferred from the external device to the DM8203
port 2 MAC reconciliation sub layer.
•
RXC2 (receive clock) from external device to
the DM8203 port 2 MAC reconciliation sub layer is a
continuous clock that provides the timing reference
for the transfer of the RXDV2, RXD2, and RXER2
signals.
The DM8203 management functions correspond
to MII specification for IEEE 802.3u-1995 (Clause 22)
for registers 0 through 6 with vendor-specific registers
16,17, 18, 21, 22, 23 and 24~27.
•
RXDV2 (receive data valid) input from the
In read/write operation, the management data
frame is 64-bits long and starts with 32 contiguous
logic one bits (preamble) synchronization clock cycles
on MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the operation
code (OP) :< 10> indicates Read operation and <01>
indicates Write operation. For read operation, a 2-bit
turnaround (TA) filing between Register Address field
and Data field is provided for MDIO to avoid
contention. Following the turnaround time, 16-bit data
is read from or written onto management registers.
external device to indicates that the external device is
presenting recovered and decoded nibbles to the
DM8203 port 2 MAC reconciliation sub layer. To
interpret a receive frame correctly by the
reconciliation sub layer, RXDV2 must encompass the
frame, starting no later than the Start-of-Frame
delimiter and excluding any End-Stream delimiter.
•
RXER2 (receive error) input from the external
device is synchronously with respect to RXC2.
RXER2 will be asserted for 1 or more clock periods to
indicate to the reconciliation sub layer that an error
was detected somewhere in the frame being
48
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
