DS3251/DS3252/DS3253/DS3254
Figure 17-4. Parallel CPU Interface Timing Diagram (Multiplexed) (continued)
MOTOROLA READ CYCLE
t13
t12
ALE
t11
ADDRESS
A[5:0]
VALID
t14
D[7:0]
DATA VALID
t14
t5
R/W
CS
DS
t4
t2
t3
t10
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
NOTE: TO AVOID BUS CONTENTION, STOP DRIVING A[5:0] BEFORE RD GOES LOW.
MOTOROLA WRITE CYCLE
t13
ALE
t12
t11
ADDRESS
VALID
A[5:0]
t14
t14
D[7:0]
t7
t8
R/W
CS
DS
t6
t2
t4
t10
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
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