2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
Status Register (0Fh)
BIT 7
BIT 6
BIT .
BIT +
BIT ꢅ
BIT ±
BIT 1
BIT ꢂ
OSF
0
0
0
EN32kHz
BSY
A2F
A1F
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Status Register (0Fh)
Biꢃ 7: Oscillaꢃꢁr Sꢃꢁ2 Flag (OSF)3 A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
Biꢃ ꢂ: Alarp 1 Flag (A1F)3 A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
1) The first time power is applied.
2) The voltages present on both V
insufficient to support oscillation.
and V
are
BAT
CC
Crystal Aging
3) The EOSC bit is turned off in battery-backed mode.
The crystal aging offset register provides an 8-bit code
to add to the codes in the capacitance array registers.
The code is encoded in two’s complement. One LSB
represents one small capacitor to be switched in or out
of the capacitance array at the crystal pins. The offset
register is added to the capacitance array register
under the following conditions: during a normal temper-
ature conversion, if the temperature changes from the
previous conversion, or during a manual user conver-
sion (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging register change.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Biꢃ ꢅ: Enable ꢅ±kHz Ouꢃ2uꢃ (ENꢅ±kHz)3 This bit indi-
cates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes to a high-impedance state. The initial power-up
state of this bit is logic 1, and a 32.768kHz square-wave
signal appears at the 32kHz pin after a power source is
applied to the DS3231 (if the oscillator is running).
Biꢃ ±: Busy (BSY)3 This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The change in ppm per LSB is different at different tem-
peratures. The frequency vs. temperature curve is shift-
ed by the values used in this register. At +25°C, one LSB
typically provides about 0.1ppm change in frequency.
Biꢃ 1: Alarp ± Flag (A±F)3 A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
Crystal Aging Offset (10h)
BIT 7
BIT 6
BIT .
BIT +
BIT ꢅ
BIT ±
BIT 1
BIT ꢂ
Sign
Data
Data
Data
Data
Data
Data
Data
1+
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DALLAS [ DALLAS SEMICONDUCTOR ]
