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DS2154LN 参数 Datasheet PDF下载

DS2154LN图片预览
型号: DS2154LN
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型E1单芯片收发器 [Enhanced E1 Single Chip Transceiver]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 87 页 / 1103 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS2154  
RECEIVE SIDE BOUNDARY TIMING  
(WITH ELASTIC STORE DISABLED) Figure 13-2  
NOTES:  
1. RCHBLK is programmed to block Channel 2.  
2. RLCLK is programmed to pulse high during the Sa4 bits position.  
3. Shown is a non-align frame boundary.  
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1.  
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING  
(WITH ELASTIC STORE ENABLED) Figure 13-3  
NOTES:  
1. Data from the E1 Channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (Channel 2 from the E1 link is  
mapped to Channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1).  
2. RSYNC is in the output mode (RCR1.5=0).  
3. RSYNC is in the input mode (RCR1.5=1).  
4. RCHBLK is programmed to block Channel 24.  
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