DS2154
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per-Channel Loopback]
(MSB)
(LSB)
CH8
CH16
CH24
CH32
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
CH9
CH17
CH25
SYMBOL
POSITION NAME AND DESCRIPTION
CH32
TIR4.7
TIR1.0
Transmit Idle Registers.
0=do not insert the Idle Code in the TIDR into this channel
CH1
1=insert the Idle Code in the TIDR into this channel
NOTE:
If CCR3.5=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback;
see Figure 1-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION NAME AND DESCRIPTION
TIDR7
TIDR0
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
8.1.2 Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code
to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel 1 is shown; see Table 1-3 for other register address)
(MSB)
(LSB)
C7
C6
SYMBOL
C7
C5
POSITION NAME AND DESCRIPTION
TC1.7 MSB of the Code (this bit is transmitted first)
C4
C3
C2
C1
C0
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DALLAS [ DALLAS SEMICONDUCTOR ]
