DS2154
5.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(LSB)
(note 1) (note 1) (note 1) (note 1) (note 1)
(note 1)
CRC2
CRC9
CRC1
CRC8
CRCCR1
CRCCR2
CRC7
CRC6
CRC5
CRC4
CRC3
CRC0
SYMBOL
CRC9
POSITION NAME AND DESCRIPTION
CRCCR1.1
CRCCR2.0
MSB of the 10-bit CRC4 error count.
LSB of the 10-bit CRC4 error count.
CRC0
NOTE:
1. The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error
counter.
5.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(LSB)
(note 1)
(note 1)
EB6
(note 1)
EB5
(note 1)
EB4
(note 1)
EB3
(note 1)
EB2
EB9
EB1
EB8
EBCR1
EBCR2
EB7
EB0
SYMBOL
POSITION NAME AND DESCRIPTION
EB9
EB0
EBCR1.1
EBCR2.0
MSB of the 10-bit E-Bit count.
LSB of the 10-bit E-Bit count.
NOTE:
The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
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DALLAS [ DALLAS SEMICONDUCTOR ]
