DS2152
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
(LSB)
RFDL
TFM
TB8ZS
TSLC96
TFDL
RFM
RB8ZS
RSLC96
SYMBOL
POSITION NAME AND DESCRIPTION
TFM
CCR2.7
CCR2.6
CCR2.5
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZS
TSLC96
Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
Transmit SLC-96 / Fs-Bit Loading Enable. Only set this bit to
a 1 in D4 framing applications. Must be set to 1 to source the Fs
pattern. See Section 11 for details.
0 = SLC-96/Fs-bit loading disabled
1 = SLC-96/Fs-bit loading enabled
TFDL
CCR2.4
Transmit FDL 0 Stuffer Enable. Set this bit to 0 if using the
internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 11 for details.
0 = 0 stuffer disabled
1 = 0 stuffer enabled
RFM
CCR2.3
CCR2.2
CCR2.1
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZS
RSLC96
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
Receive SLC-96 Enable. Only set this bit to a 1 in D4/SLC-96
framing applications. See Section 11 for details.
0 = SLC-96 disabled
1 = SLC-96 enabled
RFDL
CCR2.0
Receive FDL 0 Destuffer Enable. Set this bit to 0 if using the
internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 11 for details.
0 = 0 destuffer disabled
1 = 0 destuffer enabled
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DALLAS [ DALLAS SEMICONDUCTOR ]
