DS2152
Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered clock from the T1 line. This pin is normally tied
to RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is
normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
PARALLEL CONTROL PORT PINS
Interrupt [INT]. Flags host controller during conditions and change of conditions defined in the Status
Registers 1 and 2 and the FDL Status Register. Active low, open drain output.
3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set
low for normal operation. Useful in board-level testing.
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX =
0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A6]. In non-multiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these
pins assume the function listed in parenthesis ().
Read Input [RD ] (Data Strobe [ DS ]). RD and DS are active low signals when MUX=1. DS is active
high when MUX = 0. See bus timing diagrams.
Chip Select [CS ]. Must be low to read or write to the device. CS is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation (MUX =
0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus
on a positive-going edge.
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DALLAS [ DALLAS SEMICONDUCTOR ]
