DS2152
at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output
double-wide pulses at signaling frames. See Section 15 for details.
Transmit System Sync [TSSYNC]. Only used when the transmit side elastic store is enabled. A pulse at
this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in
applications that do not use the transmit side elastic store.
Transmit Signaling Input [TSIG]. When enabled, this input will sample signaling bits for insertion into
outgoing PCM T1 data stream. Sampled on the falling edge of TCLK when the transmit side elastic store
is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Transmit Elastic Store Data Output [TESO]. Updated on the rising edge of TCLK with data out of the
transmit side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA.
Transmit Data [TDATA]. Sampled on the falling edge of TCLK with data to be clocked through the
transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO]. Updated on the rising edge of TCLKO with the bipolar data
out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format
(CCR1.6) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated on the rising edge of TCLKO with the bipolar
data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output [TCLKO]. Buffered clock that is used to clock data through the transmit side
formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high.
TPOSI and TNEGI can be tied together in NRZ applications.
Transmit Negative Data Input [TNEGI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high.
TPOSI and TNEGI can be tied together in NRZ applications.
Transmit Clock Input [TCLKI]. Line interface transmit clock. Can be internally connected to TCLKO
by tying the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one
RCLK before the start of a frame. See Section 15 for details.
Receive Link Clock [RLCLK]. A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output.
Receive Clock [RCLK]. 1.544 MHz clock that is used to clock data through the receive side framer.
Receive Channel Clock [RCHCLK]. A 192 kHz clock which pulses high during the LSB of each
channel. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with
RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial conversion of
channel data.
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DALLAS [ DALLAS SEMICONDUCTOR ]
