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DS1339U-33+ 参数 Datasheet PDF下载

DS1339U-33+图片预览
型号: DS1339U-33+
PDF下载: 下载PDF文件 查看货源
内容描述: I²C串行实时时钟 [I2C Serial Real-Time Clock]
分类和应用: 外围集成电路光电二极管时钟
文件页数/大小: 18 页 / 280 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS1339 I2C Serial Real-Time Clock  
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output  
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2  
registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a  
square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.  
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the  
status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0,  
the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.  
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the  
status register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0,  
the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.  
STATUS REGISTER (0Fh)  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
OSF  
0
0
0
0
0
A2F  
A1F  
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped  
for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered  
and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit  
to be set:  
1) The first time power is applied.  
2) The voltage on both VCC and VBACKUP are insufficient to support oscillation.  
3) The EOSC bit is turned off.  
4) External influences on the crystal (e.g., noise, leakage, etc.).  
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.  
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If  
the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared  
when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value  
unchanged.  
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If  
the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared  
when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value  
unchanged.  
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