DS1307/1308
DS1307 ADDRESS MAP
Figure 2
00H
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
07H
08H
CONTROL
RAM
56 x 8
3FH
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the
appropriate register bytes. The contents of the time and calendar registers are in the Binary-Coded
Decimal (BCD) format. Bit 7 of Register 0 is the Clock Halt (CH) bit. When this bit is set to a 1, the
oscillator is disabled. When cleared to a 0, the oscillator is enabled.
Please note that the initial power on state of all registers is not defined. Therefore it is important to
enable the oscillator (CH bit=0) during initial configuration.
The DS1307/DS1308 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined
as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit
5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-23
hours).
On a 2-wire START, the current time is transferred to a second set of registers. The time information is
read from these secondary registers, while the clock may continue to run. This eliminates the need to re-
read the registers in case of an update of the main registers during a read.
DS1307/DS1308 TIMEKEEPER REGISTERS
Figure 3
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DALLAS [ DALLAS SEMICONDUCTOR ]
