DS1307
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or -40°C to +85°C; V
CC
=4.5V to 5.5V)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
Capacitive Load for each Bus Line
I/O Capacitance
Crystal Specified Load Capacitance
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
C
B
C
I/O
MIN
0
4.7
4.0
4.7
4.0
4.7
0
250
1000
300
4.7
400
10
12.5
TYP
MAX
100
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
pF
pF
NOTES
5
6, 7
8
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All voltages are referenced to ground.
Logic zero voltages are specified at a sink current of 5 mA at V
CC
=4.5V, V
OL
=GND for capacitive
loads.
I
CCS
specified with V
CC
=5.0V and SDA, SCL=5.0V.
V
CC
=0V, V
BAT
=3V.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
IHMIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
C
B
- total capacitance of one bus line in pF.
I
CCA
- SCL clocking at max frequency = 100 kHz.
10. SCL only.
11. SDA and SQW/OUT
9 of 11
DALLAS [ DALLAS SEMICONDUCTOR ]
